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preliminary w742e81a/W742C81A 4 - bit microcontrolle r publication release date: april 2000 - 1 - revision a1 1. general description the w742e81a/W742C81A is a high - performance 4 - bit microcontroller ( m c) that provides an lcd driver. the device contains a 4 - bit alu, two 8 - bit timers, two dividers (for two oscillators) in dual - clock operation, a 40 4 lcd driver, six 4 - bit i/o ports (including 1 output port for led driving), and one channel dtmf generator. there are also five interrupt sources and 16 - levels subroutine nesting for interrupt applications. the w742e81a/W742C81A operates on very low current and has two pow er reduction modes, that is the dual - clock slow operation and stop mode, which help to minimize power dissipation. 2. features operating voltage: 2.4v - 3.8v dual - clock operation or single - clock operation (by option) main - oscillator - connect to 3.58 mh z crystal or 400 khz that can be selected by option code - crystal or rc oscillator can be selected by code option (w742e81a) - connect to 2 mhz typical rc oscillator (W742C81A) sub - oscillator - connect to 32768 hz crystal only memory - 16384 x 1 6 bits program flash eeprom (including 64k x 4 bit look - up table) - 2048 x 4 bits data ram (including 16 nibbles x 16 pages working registers) - 40 x 4 lcd data ram 24 input/output pins - port for input only: 1 ports/4 pins(rc) - input/output ports : 3 ports/12 pins(ra, rb & rd) - high sink current output port for led driving: 1 port /4 pins(re) - port for output only: 1 port/ 4 pins(rf) power - down mode - hold function: no operation (main - oscillator and sub - oscillator still operate) - stop fu nction: no operation (main - oscillator and sub - oscillator are stopped) - dual - clock slow operation mode: system is operated by the sub - oscillator (f osc =fs and fm is stopped) five types of interrupts - four internal interrupts (divider0, divider1, ti mer 0, timer 1) - one external interrupts (rc port)
preliminary w742e81a/W742C81A - 2 - lcd driver output - 40 segments x 4 commons - 1/4 duty 1/3 bias driving mode - clock source should be the sub - oscillator clock in the dual - clock operation mode mfp output pin - output is software selectable as modulating or nonmodulating frequency - works as frequency output specified by timer 1 dtmf output pin - output is one channel dual tone multi - frequency signal for dialling two built - in 14 - bit frequency dividers - divider0: the clock source is the output of the main - oscillator - divider1: the clock source is the output of the sub - oscillator (dual - clock mode) or the fosc/128 (single - clock mode) two built - in 8 - bit programmable countdown timers - timer 0: on e of two internal clock frequencies (f osc /4 or f osc /1024) can be selected - timer 1: with auto - reload function and one of three internal clock frequencies (f osc, f osc /64 or fs) can be selected by mr1 register; and the specified frequency can be deli vered to mfp pin built - in 18/15 - bit watchdog timer selectable for system reset; enable the watch dog timer or not is determined by code option powerf ul instruction set: 142 instructions 16 - levels subroutine (include interrupt) nesting
preliminary w742e81a/W742C81A publication release date : april 2000 - 3 - revision a1 3. pin configuration for w742e81a 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36 37 38 39 40 41 42 43 44 45 46 47 48 81 82 83 84 85 86 87 88 89 90 91 92 rc1 rc0 rb3 rb2 rb1 rb0 ra3 ra1 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 r e 1 r e 2 seg22 seg21 seg20 seg19 ra0 ra2 20 21 22 23 24 49 50 61 60 59 58 57 93 94 95 n c nc rd0 rc3 rc2 25 26 27 28 29 56 55 54 53 52 96 97 rd2 rd1 98 99 100 nc rd3 31 32 33 34 35 seg18 seg17 seg16 seg15 n c r e 0 r e 3 r f 0 r f 1 r f 2 r f 3 v s s s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 n c n c n c 51 30 n c n c n c s e g 3 3 s e g 3 4 s e g 3 5 s e g 3 6 s e g 3 7 s e g 3 8 s e g 3 9 c o m 3 c o m 2 c o m 1 c o m 0 v d d 2 v d d 1 d h 2 d h 1 x o u t 2 x i n 2 v d d x o u t 1 x i n 1 d t m f r e s n c n c n c s e g 1 4 nc s e g 3 2 mfp nc nc n c nc n c
preliminary w742e81a/W742C81A - 4 - for w742c810 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36 37 38 39 40 41 42 43 44 45 46 47 48 81 82 83 84 85 86 87 88 89 90 91 92 rc1 rc0 rb3 rb2 rb1 rb0 ra3 ra1 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 r e 1 r e 2 seg22 seg21 seg20 seg19 ra0 ra2 20 21 22 23 24 49 50 61 60 59 58 57 93 94 95 n c nc rd0 rc3 rc2 25 26 27 28 29 56 55 54 53 52 96 97 rd2 rd1 98 99 100 nc rd3 31 32 33 34 35 seg18 seg17 seg16 seg15 n c r e 3 r f 0 r f 1 r f 2 r f 3 v s s s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 s e g 5 s e g 6 s e g 7 s e g 8 s e g 9 s e g 1 0 s e g 1 1 s e g 1 2 s e g 1 3 n c n c n c 51 30 n c n c n c s e g 3 3 s e g 3 4 s e g 3 5 s e g 3 6 s e g 3 7 s e g 3 8 s e g 3 9 c o m 3 c o m 2 c o m 1 c o m 0 v d d 2 v d d 1 d h 2 d h 1 x o u t 2 x i n 2 v d d x o u t 1 x i n 1 d t m f r e s n c n c n c mfp n c nc n c re0 n c seg14 n c seg32 n c
preliminary w742e81a/W742C81A publication release date : april 2000 - 5 - revision a1 4. pin description symbol i/o functi on xin2 i input pin for sub - oscillator. connected to 32.768 khz crystal only. xout2 o output pin for sub - oscillator with internal oscillation capacitor. connected to 32.768 khz crystal only. xin1 i input pin for main - oscillator. connected to 3.58 mhz o r 400 khz crystal or rc to generate system clock. xout1 o output pin for main - oscillator. connected to 3.58 mhz or 400 khz crystal or rc to generate system clock. ra0 - ra3 i/o input/output port. input/output mode specified by port mode 1 register (pm1). rb0 - rb3 i/o input/output port. input/output mode specified by port mode 2 register (pm2). rc0 - rc3 i 4 - bit port for input only. each pin has an independent interrupt capability. rd0 - rd3 i/o input/output port. input/output mode specified by port mode 5 re gister (pm5). re0 - re3 o output port only. with high sink current capacity for the led application. rf0 - rf3 o output port only. mfp o output pin only. this pin can output modulating or nonmodulating frequency, or timer 1 specified frequen cy. it can be selected by bit 0 of buzcr (buzcr.0). dtmf o this pin can output dual - tone multifrequency signal for dialling. res i system reset pin with pull - high resistor. seg0 - seg39 o lcd segment output pins. com0 - com3 o lcd common signal output pins. the lcd alternating frequency can be selected by code option. dh1, dh2 i connection terminals for voltage doubler (halver) capacitor. v dd1 v dd2 i positive (+) supply voltage terminal. refer to functional description. v dd i positiv e power supply (+). v ss i negative power supply ( - ).
preliminary w742e81a/W742C81A - 6 - pin description, continued symbol i/o function v pp i voltage control pin for the flash eeprom programming, erasing and verifying. this pin has the built - in pull - low resistor. mode i this pin c an be used as mode selection control; data read/write clock; program/erase control or address counter control in the flash eeprom erasing, programming or verifying mode. this pin has the built - in pull - low resistor. data i/o data i/o pin with the built - i n pull - low resistor. 5. block diagram lcd driver pc stack (16 levels) ram (2048*4) alu timer 0 (8 bit) timing generator port ra port rb port rc modulation frequency pulse seg0~seg39 com0~com3 ra0-3 rb0-3 rc0-3 rd0-3 mfp xin1 xout1 xin2 xout2 vdd vss vdd1-2 dh1-2 flash eerom (16384*16) (look_up table 64k*4) timer 1 (8 bit) acc res divider 0 (14 bit) watch dog timer (4 bit) hcf pef hef ief central control unit evf sef psr0 scr pr mr0 mr1 . . . port re mux sel +1(+2) port rd pm0 divider 1 (12/14 bit) re0-3 port rf rf0-3 dtmf generator dtmf pm1 dtmf dtcr vpp data mode
preliminary w742e81a/W742C81A publication release date : april 2000 - 7 - revision a1 6. functional descripti on 6.1 program counter (pc) organized as an 14 - bit binary counter (pc0 to pc13), the program counter generates the addresses of the 16384 16 on - chip rom containing t he program instruction words. before the jump or subroutine call instructions are to be executed, the destination rom page must be determined firstly. the confirmation of the rom page can be done by executing the mov rompr, #i or mov rompr, r instruction. when the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. the format used is shown below. table 1 vector address and interrupt priority item addre ss interrupt priority initial reset 0000h - int 0 (divider0) 0004h 1st int 1 (timer 0) 0008h 2nd int 2 (port rc) 000ch 3rd int 3 (divider1) 0014h 4th int 4 (timer 1) 0020h 5th jp instruction xxxxh - subroutine call xxxxh - 6.2 stack register (stack) the stack register is organized as 49 bits x 16 levels (first - in, last - out). when either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. at the end of a call subroutine or an interrup t service subroutine, the rtn instruction must be executed to pop the contents of the stack register into the program counter. (refer to table 8) when the stack register is pushed over the sixteen levels, the contents of the first level will be lost. in other words, the stack register is always sixteen levels deep. 6.3 program memory (rom) the read - only memory (rom) is used to store program codes; and the look - up table is arranged as 65536 x 4 bits. the program rom is divided into eight pages; the size of each page is 2048 x 16 bits. so the total rom size is 16384 x 16 bits. before the jump or subroutine call instructions are to be executed, the destination rom page must be determined firstly. the rom page can be selected by e xecuting the mov rompr,#i or mov rompr, r instruction. but the branch decision instructions (e.g. jb0, skb0, jz, jc, ...) must jump to the same rom page which the branch decision instructions are in. the whole rom can store both instruction codes and the l ook - up table. each look - up table element is composed of 4 bits, so the look - up table can be addressed up to 65536 elements. instruction movc r is used to read the look - up table content and transfer table data to the ram. but before reading the addressed lo ok - up table content, the content of the look - up table pointer (tab) must be determined firstly. the address of the look - up table element is allocated by the content of tab. the mov tab0 (tab1, tab2, tab3), r instructions are used to allocate the address of the wanted look - up table element. the tab0 register stores the lsb 4 bits of the look - up table address.
preliminary w742e81a/W742C81A - 8 - the organization of the program memory is shown in figure 6 - 1 . 0000h 16 bits 16384 x 16 bits 07ffh 0400h : : each element (4 bits) of the look-up table : 03ffh : 0800h 0fffh 0c00h : 0bffh : 1st page 3c00h : 3bffh : 3800h 3fffh 2nd page 8th page look-up table address: 0000h : 0fffh look-up table address: 1000h : 1fffh look-up table address: 2000h : 2fffh look-up table address: 3000h : 3fffh look-up table address: e000h : efffh look-up table address: f000h : ffffh : : : : figure 6 - 1 program memory organization 6.3.1 rom page register (rompr) the rom page register is organized as a 4 - bit binary register. the bit descriptions are as follows: w w 0 1 2 3 rompr w note: w means write only. bit 3 is reserved. bit 2, bit 1, bit 0 rom page preselect bits: 000 = rom page 0 (0000h - 07ffh) 001 = rom page 1 (0800h - 0fffh) 010 = rom page 2 (1000h - 17ffh) 011 = rom page 3 ( 1800h - 1fffh) 100 = rom page 4 (2000h - 27ffh) 101 = rom page 5 (2800h - 2fffh) 110 = rom page 6 (3000h - 37ffh) 111 = rom page 7 (3800h - 3fffh)
preliminary w742e81a/W742C81A publication release date : april 2000 - 9 - revision a1 6.4 data memory (ram) 6.4.1 architecture the static data memory (ram) used to store data is arranged as 2048 4 bits. the data ram is divided into sixteen banks; each bank has 128 4 bits. executing the mov dbkr,wr or mov dbkr,#i instruction can determine which data bank is used. the data memory can be addressed directly or indirectly. but the data bank must be confirmed firstly; and the page in the data bank will be done in the indirect addressing mode, too. in indirect addressing mode, each data bank will be divided into eight pages. before the data memory is addressed i ndirectly, the page which the data memory is in must be confirmed. the organization of the data memory is shown in figure 6 - 2 . 1st data bank 2048 addresses 000h 4 bits 2048 * 4 bits : 07fh 080h : 0ffh 2nd data bank : : 780h : 7ffh 16th data bank (or working registers bank) 00h : 0fh 10h : 1fh 20h : 2fh 70h : 7fh : : 1st data ram page (or 1st wr page) 2nd data ram page (or 2nd wr page) 8th data ram page (or 8th wr page) 3rd data ram page (or 3rd wr page) (or working registers bank) 3rd data bank figure 6 - 2 da ta memory organization the 1st and 2nd data bank (00h to 7fh & 80h to ffh) in the data memory can also be used as the working registers (wr). it is also divided into sixteen pages. each page contains 16 working registers. when one page is used as wr, the o thers can be used as the normal data memory. the wr page can be switched by executing the mov wrp,r or mov wrp,#i instruction. the data memory cannot operate directly with immediate data, but the wr can do. the relationship between data memory locations an d the page register (page) in indirect addressing mode is described in the next sub - section. 6.4.2 page register (page) the page register is organized as a 4 - bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 page note: r/w means read/write available. bit 3 is reserved. bit 2, bit 1, bit 0 indirect addressing mode preselect bits: 000 = page 0 (00h - 0fh)
preliminary w742e81a/W742C81A - 10 - 001 = page 1 (10h - 1fh) 010 = page 2 (20h - 2fh) 011 = page 3 (30h - 3fh) 100 = page 4 (40h - 4fh) 101 = page 5 (50h - 5fh) 110 = page 6 (60h - 6fh) 111 = page 7 (70h - 7fh) 6.4.3 wr page register (wrp) the wr page register is organized as a 4 - bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 wrp r/w note: r/w means read/write available. bit 3, bit 2, bit 1, bit 0 working registers page preselect bits: 0000 = wr page 0 (00h - 0fh) 0001 = wr page 1 (10h - 1fh) 0010 = wr page 2 (20h - 2fh) 0011 = wr page 3 (30h - 3fh) 0100 = wr page 4 (40h - 4fh) 0101 = wr page 5 (50h - 5fh) 0110 = wr page 6 (60h - 6fh) 0111 = wr page 7 (70h - 7fh) 1000 = wr page 8 (80h - 8fh) 1001 = wr page 9 (90h - 9fh) 1010 = wr page a (a0h - afh) 1011 = wr page b (b0h - bfh) 1100 = wr page c (c0h - cfh) 1101 = wr page d (d0h - dfh) 1110 = wr page e (e0h - efh) 1111 = wr page f (f0h - ffh) 6.4.4 data bank register (dbkr) the data bank register is organized as a 4 - bit binary register. the bit descriptions are as follows: r/w r/w r/w 0 1 2 3 dbkr r/w note: r/w means read/write available.
preliminary w742e81a/W742C81A publication release date : april 2000 - 11 - revision a1 bit 3, bit 2, bit 1, bit 0 data memory bank preselect bits: 0000 = data bank 0 (000h - 07fh) 0001 = data bank 1 (080h - 0ffh) 0010 = data bank 2 (100h - 17fh) 0011 = data bank 3 (180h - 1ffh) 0100 = data bank 4 (200h - 27fh) 0101 = data bank 5 (280h - 2ffh) 0110 = data bank 6 (300h - 37fh) 0111 = data bank 7 (380h - 3ffh) 1000 = data bank 8 (400h - 47fh) 1001 = data bank 9 (480h - 4ffh) 1010 = data bank a (500h - 57fh) 1011 = data bank b (580h - 5ffh) 1100 = data bank c (600h - 67fh) 1101 = data bank d (680 h - 6ffh) 1110 = data bank e (700h - 77fh) 1111 = data bank f (780h - 7ffh) 6.5 accumulator (acc) the accumulator (acc) is a 4 - bit register used to hold results from the alu and transfer data between the memory, i/o ports, and registers . 6.6 arithmetic and logic unit (alu) this is a circuit which performs arithmetic and logic operations. the alu provides the following functions: logic operations: anl, xrl, orl branch decisions: jb0, jb1, jb2, jb3, jnz, jz, jc, jnc, dskz, dsknz, skb0, s kb1, skb2, skb3 shift operations: shrc, rrc, shlc, rlc binary additions/subtractions: adc, sbc, add, sub, adu, dec, inc after any of the above instructions are executed, the status of the carry flag (cf) and zero flag (zf) is stored in the intern al registers. cf can be read out by executing mov r, cf. 6.7 main - oscillator the w742e81a/W742C81A provides a crystal or rc oscillation circuit to generate the system clock through external connections. if a crystal oscillator is used, the 3.58 mhz or 400khz c rystal must be connected to xin1 and xout1, and a capacitor must be connected to xin1 and v ss if an accurate frequency is needed.
preliminary w742e81a/W742C81A - 12 - xin1 xout1 crystal 3.58 mhz or 400 khz xin1 xout1 or figure 6 - 3 system clock oscillator configuration 6.8 sub - oscil lator the sub - oscillator is used in dual - clock operation mode. in the sub - oscillator application, just only the 32768 hz crystal could be connected to xin2 and xout2, and it would not be oscillated in stop mode. 6.9 dividers each divider is organized as a 14 - b it binary up - counter designed to generate periodic interrupts. when the main oscillator starts action, the divider0 is incremented by each clock (f osc ). when an overflow occurs, the divider0 event flag is set to 1 (evf.0 = 1). then, if the divider0 interru pt enable flag has been set (ief.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (hef.0 = 1), the hold state is terminated. and the last 4 - stage of the divider0 can be reset by executing clr divr0 instruction. if the sub - oscillator starts action, the divider1 is incremented by each clock (fs in dual - clock mode or fosc/128 in single - clock mode). when an overflow occurs, the divider1 event flag is set to 1 (evf.4 = 1). then, if the divider1 interrupt enable flag has been set (ief.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (hef.4 = 1), the hold state is terminated. and the last 4 - stage of the divider1 can be reset by executing clr divr1 instruction. same as evf.0, the evf.4 is set to 1 periodically. but there are two period time (125 ms & 500ms) that can be selected by setting the scr.3 bit. when scr.3 = 0 (default), the 500 ms period time is selected; scr.3 = 1, the 125 ms period time is selected. 6.10 dual - clock operation this operat ion mode is selected by option code. in the dual - clock mode, the clock source of the lcd frequency selector should be the sub - oscillator clock (32768 hz) only. but in the signal - clock mode, the clock source of the lcd frequency selector will be fm/128(fm : main oscillator clock, see figure 6 - 4). so before the stop instruction is executing, the lcd must be turned off in the signal - clock mode or dual - clock mode . in this dual - clock mode, the normal operation is performed by generating the system clock from th e main - oscillator clock (fm). as required, the slow operation can be performed by generating the system clock from the sub - oscillator clock (fs). the exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the system clock control register (scr). if the scr.0 is reset to 0, the clock source of the system clock generator is main - oscillator clock; if the scr.0 is set to 1, the clock source of the system clock generator is sub - oscillator clock. in the dual - cloc k mode, the main - oscillator can stop oscillating when the stop instruction is executing or the scr.1 is set to 1.
preliminary w742e81a/W742C81A publication release date : april 2000 - 13 - revision a1 when the scr is set or reset, we must care the following cases: 1. x000b ? x011b: we should not exchange the f osc from fm into fs and disable fm simultaneously. we could first exchange the f osc from fm into fs, then disable the main - oscillator. so it should be x000b ? x001b ? x011b. 2. x011b ? x000b: we should not enable fm and exchange the f osc from fs into fm simultaneously. we could first enable the main - oscillator; the 2nd step is calling a delay subroutine to wait the main - oscillator oscillating stably; then exchange the f osc from fs into fm is the last step. so it should be x011b ? x001b ? delay the fm oscillating stably time ? x000b. the suggestion of the fm oscillating stably time is 3.5 ms for 455 khz and 0.8ms for 4 mhz. we must remember that the x010b state is inhibitive, because it will induce the system shutdown. the organization of the dual - clock operation mode is shown in figure 6 - 4 . system clock generator t1 t2 t3 t4 main oscillator xin1 xout1 sub-oscillator xin2 xout2 fosc divider 0 scr : system clock control register ( default = 00h ) bit0 bit1 bit3 0 : fosc = fm 1 : fosc = fs 0 : fm enable 1 : fm disable fm fs enable/disable scr.1 stop hold scr.0 lcd frequency selector f lcd divider 1 int4 hcf.4 scr.3(14/12 bit) 1 : 12 bit 0 : 14 bit daul clock operation mode : - scr.0=0, fosc=fm : scr.0=1, fosc=fs - flcd=fs, in stop mode lcd work continue. fosc/128 dual/single colck option code is 1/0 fs or fosc/128 figure 6 - 4 organization of the dual - clock operation mode
preliminary w742e81a/W742C81A - 14 - 6.11 watchdog timer (wdt) and watchdog timer register(wdtr) the watchdog timer (wdt) is organized as a 4 - bit u p counter designed to prevent the program from unknown errors. when the corresponding option code bit of the wdt set to 1, the wdt is enabled, and if the wdt overflows, the chip will be reset. at initial reset, the input clock of the wdt is f osc /2048. the input clock of the wdt can be switched to f osc /16384 (or f osc /2048) by setting wdtr.3 to 1. the contents of the wdt can be reset by the instruction clr wdt. in normal operation, the application program must reset wdt before it overflows. a wdt overflow ind icates that operation is not under control and the chip will be reset. the wdt overflow period is 1 s when the sub - system clock (fs) is 32 khz and wdt clock input is fs/2048. when the corresponding option code bit of the wdt set to 0, the wdt function is d isabled. the organization of the divider0 and watchdog timer is shown in figure 6 - 5 . q1 q2 q9 q10 q11 q12 q14 q13 fosc s r q hef.0 ief.0 1. reset 2. clr evf,#01h evf.0 hold mode release (hcf.0) divider interrupt (int0) ... overflow signal wdt enable disable wdtr.3 fosc/2048 fosc/16384 option code is "0" qw1 qw2 qw4 qw3 r r r r divider0 system reset 1. reset 2. clr wdt 3. clr divr0 option code is "1" wdtr.2 q1 q2 q9 q10 q11 q12 q14 q13 s r q hef.4 ief.4 1. reset evf.4 hold mode release (hcf.4) divider interrupt (int1) ... divider1 fss/2048 fss/16384 2. clr evf,#10h 3. clr divr1 fss=fs or fosc/128 scr.3 figure 6 - 5 organization of divider0, divider1 and watc hdog timer
preliminary w742e81a/W742C81A publication release date : april 2000 - 15 - revision a1 0 1 2 3 wdtr r/w r/w r/w r note: r/w means read/write available, r means read only. power on reset default is : 0000 bit 3 = 0 f osc/ 2048(select divider0) or fss/2048(select divider1) as the wdt source. = 1 f osc/ 16384(select divider0) or fss/16384(select divider1) as the wdt source. bit 2 = 0 select divider0. = 1 select divider1. bit 1 = 0 refer to table 2 . = 1 refer to table 2 . bit 0 = 0 no time out. = 1 time out. wdtr.0 will be set to one when wdt time out and can be reset to zero by: power on reset, reset pin, clr wdt table 2 the bit 1 of watchdog timer register (wdtr) r eset item reset item wdtr.1 = 1 wdtr.1 = 0 program counter (pc) 0000h 0000h stack pointer (sp) - reset rompr, page, dbkr, wrp, acc, cf, zf, scr registers - reset ief, hef, sef, hcf, pef, evf flags ief = reset reset div0, div1 - reset tm0, tm1, mr0, m r1 registers - reset timer 0 input clock - fosc/4 timer 1 input clock - fosc mfp output - low pm0 register - reset pm1, pm2, pm5 registers - set (1111b) psr0 register - reset input/output ports ra, rb, rd - input mode output ports re, rf - high r a, rb ports output type - cmos type rc port pull - high resistors - disable input clock of the watchdog timer - fosc/2048 dtmf output - hi - z buzcr register - reset flcd - q5 to q9 reset lcd display - off lcdr - reset segment output mode - lcd drive output - : keep the status note: scr.2 is reserved
preliminary w742e81a/W742C81A - 16 - 6.12 timer/counter 6.12.1 timer 0 (tm0) timer 0 (tm0) is a programmable 8 - bit binary down - counter. the specified value can be loaded into tm0 by executing the mov tm0l(tm0h),r instructions. when the mov tm0l(tm0h),r i nstructions are executed, it will stop the tm0 down - counting (if the tm0 is down - counting) and reset the mr0.3 to 0, and the specified value can be loaded into tm0. then we can set mr0.3 to 1, that will cause the event flag 1 (evf.1) is reset and the tm0 s tarts to count. when it decreases and underflow to ffh, timer 0 stops operating and generates an underflow (evf.1 = 1). then, if the timer 0 interrupt enable flag has been set (ief.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (hef.1 = 1), the hold state is terminated. the timer 0 clock input can be set as f osc /1024 or f osc /4 by setting mr0.0 to 1 or resetting mr0.0 to 0. the default timer value is f osc /4. the organization of timer 0 is shown in figure 6 - 6 . if the timer 0 clock input is f osc /4: desired timer 0 interval = (preset value +1) 4 1/f osc if the timer 0 clock input is f osc /1024: desired timer 0 interval = (preset value +1) 1024 1/f osc preset value: decimal numb er of timer 0 preset value f osc : clock oscillation frequency fosc/4 fosc/1024 enable disable 1. reset 2. clr evf,#02h 8-bit binary down counter s r q hef.1 ief.1 hold mode release (hcf.1) timer 0 interrupt (int1) 1. reset 2. clr evf,#02h evf.1 mr0.0 (timer 0) set mr0.3 to 1 3. reset mr0.3 to 0 3.set mr0.3 to 1 4 4 mov tm0h,r mov tm0l,r 4.mov tm0l,r or mov tm0h,r figure 6 - 6 organization of timer 0
preliminary w742e81a/W742C81A publication release date : april 2000 - 1 7 - revision a1 6.12.2 timer 1 (tm1) timer 1 (tm1) is also a programmable 8 - bit binary down counter, a s shown in figure 6 - 7 . timer 1 can be used as to output an arbitrary frequency to the mfp pin. the input clock of timer 1 can be one of three sources: f osc /64, f osc , or fs. the source can be selected by setting bit 0 a nd bit 1 of mode register 1 (mr1). at initial reset, the timer 1 clock input is f osc . when the mov tm1l, r or mov tm1h,r instruction is executed, the specified data are loaded into the auto - reload buffer; but the tm1 down - counting will keep going on. if th e bit 3 of mr1 is set (mr1.3 = 1), the content of the auto - reload buffer will be loaded into the tm1 down counter, and timer 1 starts to down count, and the event flag 7 is reset (evf.7 = 0). when the timer decreases and underflow to ffh, it will generate an underflow (evf.7 = 1) and be auto - reloaded with the specified data, after which it will continue to count down. then, if interrupt enable flag 7 has been set to 1 (ief.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (hef .7 = 1), the hold state is terminated. the specified frequency of timer 1 can be delivered to the mfp output pin by programming bit 2 of mr1. bit 3 of mr1 can be used to make timer 1 stop or start counting. in a case where timer 1 clock input is f t : desired timer 1 interval = (preset value +1) / f t desired frequency for mfp output pin = f t ? (preset value + 1) ? 2 (hz) preset value: decimal number of timer 1 preset value f osc : clock oscillation frequency auto-reload buffer 8 bits mr1.3 underflow signal evf.7 mfp mfp signal buzcr.0 output pin 8-bit binary down counter 2 circuit reset reset disable enable fosc/64 fosc mr1.0 (timer 1) s r q 1. reset 2. int7 accept 3. clr evf, #80h t f 4. set mr1.3 to 1 4 4 mov tm1h,r mov tm1l,r set mr1.3 to 1 mr1.1 fs mov wr,tm1 8 bits figure 6 - 7 organization of timer 1
preliminary w742e81a/W742C81A - 18 - for example, when f t equals 32768 hz, depending on the preset value of tm1, the mfp pin will output a single tone signal in the tone frequency range from 64 hz to 16384 hz. the relation betw een the tone frequency and the preset value of tm1 is shown in the table below. mov wr,tm1 can read back the content of tm1, it will save the tm1 msb to wr and the tm1 lsb to acc. table 3 the relation between the tone frequency an d the present value of tm1 c c # b g f e d a # # d # # g f a e n o t tm1 preset value & mfp frequency 3rd octave 4th octave 5th octave 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 3eh 3ah 37h 34h 31h 2eh 2bh 29h 26h 22h 24h 20h 468.11 496.48 1eh 1ch 1bh 19h 18h 16h 15h 14h 13h 12h 11h 10h 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 7ch 75h 6fh 68h 62h 5dh 58h 53h 4eh 45h 49h 41h 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 tone frequency tone frequency tm1 preset value & mfp frequency tone frequency tm1 preset value & mfp frequency not e: central tone is a4 (440 hz). 6.12.3 mode register 0 (mr0) mode register 0 is organized as a 4 - bit binary register (mr0.0 to mr0.3). mr0 can be used to control the operation of timer 0. the bit desc riptions are as follows: w w 0 1 2 3 mr0 note: w means write only. bit 0 = 0 the fundamental frequency of timer 0 is f osc /4. = 1 the fundamental frequency of timer 0 is f osc /1024. bit 1 & bit 2 are res erved bit 3 = 0 timer 0 stops down - counting. = 1 timer 0 starts down - counting.
preliminary w742e81a/W742C81A publication release date : april 2000 - 19 - revision a1 6.12.4 mode register 1 (mr1) & mfp control pin (buzcr) mode register 1 is organized as a 4 - bit binary register (mr1.0 to mr1.3). mr1 can be used to control the operation of timer 1. the bit descriptions are as follows: w w w w 0 1 2 3 mr1 note: w means write only. bit 0 = 0 the internal fundamental frequency of timer 1 is f osc . = 1 the internal fundamental frequency of timer 1 is f osc /64. bit 1 = 0 the fundamental frequency source of timer 1 is the internal clock. = 1 the fundamental frequency source of timer 1 is the sub - oscillator frequency fs (32768 hz). bit 2 is reserved. bit 3 = 0 timer 1 stops down - counti ng. = 1 timer 1 starts down - counting. mfp control pin is organized as a 4 - bit binary register. w 0 1 2 3 buzcr note: w means write only. bit 0 = 0 the specified waveform of the mfp generator is del ivered to the mfp output pin. = 1 the specified frequency of timer 1 is delivered to the mfp output pin. bit 1, bit 2 & bit 3 are reserved. 6.13 interrupts the w742e81a/W742C81A provides four internal interrupt sources (divider 0, divider 1, timer 0, timer 1) and one external interrupt source (port rc). vector addresses for each of the interrupts are located in the range of program memory (rom) addresses 004h to 020h. the flags ief, pef, and evf are used to control the interrupts. when evf is set to "1" by hardware and the corresponding bits of ief and pef have been set by software, an interrupt is generated. when an interrupt occurs, all of the interrupts are inhibited until the en int or mov ief,#i instruction is invoked. the interrupts can also be disable d by executing the dis int instruction. when an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. after the rtn instruction is executed in an interrupt subroutine, the m c will enter h old mode again. the operation flow chart is shown in figure 6 - 9 . the control diagram is shown in figure 6 - 9 .
preliminary w742e81a/W742C81A - 20 - s r q s r q s r q ief.0 ief.1 interrupt process circuit interrupt vector generator 004h 008h 020h ief.7 initial reset clr evf,#i instruction dis int instruction initial reset mov ief,#i enable en int evf.1 evf.0 evf.7 disable divider 0 overflow signal timer 0 underflow signal timer 1 underflow signal s r q ief.2 evf.2 rc port s r q ief.4 evf.4 overflow signal signal change 00ch divider 1 014h figure 6 - 8 interrupt event control diagram 6.14 stop mode operation in stop mode, all operations of the m c cease, and the mfp pin is kept to high. the m c enters stop mode when the stop instruction is executed and exits stop mode when an external trigge r is activated (by a falling signal on the rc). when the designated signal is accepted, the m c awakens and executes the next instruction. to prevent erroneous execution, the nop instruction should follow the stop command. but in the dual - clock slow operati on mode, the stop instruction will also disable the sub - oscillator oscillating; all operations of the m c cease. 6.14.1 stop mode wake - up enable flag for rc port (sef) the stop mode wake - up flag for port rc is organized as an 4 - bit binary register (sef.0 to sef. 3). before port rc may be used to make the device exit the stop mode, the content of the sef must be set first. the sef is controlled by the mov sef, #i instruction. the bit descriptions are as follows: sef w w w 0 1 2 w 3 note: w means write only. sef.0 = 1 device will exit stop mode when falling edge signal is applied to pin rc.0 sef.1 = 1 device will exit stop mode when falling edge signal is applied to pin rc.1
preliminary w742e81a/W742C81A publication release date : april 2000 - 21 - revision a1 sef.2 = 1 device will exit stop mode when falling edge signal is applied to pin rc.2 sef.3 = 1 device will exit stop mode when falling edge signal is applied to pin rc.3 6.15 hold mode operation in hold mode, all operations of the m c cease, except for the operation of the oscillator, timer, divider , lcd driver, dtmf generator and mfp generator. the m c enters hold mode when the hold instruction is executed. the hold mode can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1, the rc port. before the device enters the hold mode, the hef, pef, and ief flags must be set to define the hold mode release conditions. for more details, refer to the instruction - set table and the following flow chart. divider 0, divider 1, timer 0, timer 1, signal change at rc port in hold mode? ief flag set? pc <- (pc+1) ief flag set? no yes no yes yes no yes no hold hef flag set? reset evf flag execute interrupt service routine reset evf flag execute interrupt service routine interrupt enable? interrupt enable? yes yes no no disable interrupt disable interrupt (note) (note) note: the bit of evf corresponding to the interrupt signal will be reset. figure 6 - 9 hold mode and interrupt operation flow chart
preliminary w742e81a/W742C81A - 22 - 6.15.1 hold mode release enable flag (hef) the hold mode release enable flag is organized as an 8 - bit binary register (hef.0 to hef.7). the hef is used to control the hold mode release conditions. it is controlle d by the mov hef, #i instruction. the bit descriptions are as follows: w 0 1 2 hef w w w w 3 4 5 6 7 note: w means write only. hef.0 = 1 overflow from the divider 0 causes hold mode to be released. hef.1 = 1 underflow from t imer 0 causes hold mode to be released. hef.2 = 1 signal change at port rc causes hold mode to be released. hef.3, hef.5 & hef.6 are reserved. hef.4 = 1 overflow from the divider 1 causes hold mode to be released. hef.7 = 1 underflow from timer 1 cau ses hold mode to be released. 6.15.2 interrupt enable flag (ief) the interrupt enable flag is organized as a 8 - bit binary register (ief.0 to ief.7). these bits are used to control the interrupt conditions. it is controlled by the mov ief, #i instruction. when o ne of these interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are unaffected. in interrupt subroutine, these interrupts will be disable till the instruction mov ief, #i or en int is executed again. oth erwise, these interrupts can be disable by executing dis int instruction. the bit descriptions are as follows: w 1 2 3 ief 4 w w 5 6 0 w w 7 note: w means write only. ief.0 = 1 interrupt 0 is accepted by overflow from the divi der 0. ief.1 = 1 interrupt 1 is accepted by underflow from the timer 0. ief.2 = 1 interrupt 2 is accepted by a signal change at port rc. ief.3, ief.5 & ief.6 are reserved. ief.4 = 1 interrupt 4 is accepted by overflow from the divider 1. ief.7 = 1 interrupt 7 is accepted by underflow from timer 1. 6.15.3 port enable flag (pef) the port enable flag is organized as 4 - bit binary register (pef.0 to pef.3). before port rc may be used to release the hold mode or preform interrupt function, the content of the pef must be set first. the pef is controlled by the mov pef, #i instruction. the bit descriptions are as follows:
preliminary w742e81a/W742C81A publication release date : april 2000 - 23 - revision a1 pef w w w 0 1 2 w 3 note: w means write only. pef.0: enable/disable the signal change at pin rc.0 to re lease hold mode or perform interrupt. pef.1: enable/disable the signal change at pin rc.1 to release hold mode or perform interrupt. pef.2: enable/disable the signal change at pin rc.2 to release hold mode or perform interrupt. pef.3: enable/disable the si gnal change at pin rc.3 to release hold mode or perform interrupt. 6.15.4 hold mode release condition flag (hcf) the hold mode release condition flag is organized as a 8 - bit binary register (hcf.0 to hcf.7). it indicates by which interrupt source the hold mode ha s been released, and is loaded by hardware. the hcf can be read out by the mova r, hcfl and mova r, hcfh instructions. when any of the hcf bits is "1," the hold mode will be released and the hold instruction is invalid. the hcf can be reset by the clr evf or mov hef,#i (hef = 0) instructions. when evf and hef have been reset, the corresponding bit of hcf is reset simultaneously. the bit descriptions are as follows: r r hcf 0 1 2 3 4 5 r r r 6 7 note: r means read only. hcf. 0 = 1 hold mode was released by overflow from the divider 0. hcf.1 = 1 hold mode was released by underflow from the timer 0. hcf.2 = 1 hold mode was released by a signal change at port rc. hcf.3 is reserved. hcf.4 = 1 hold mode was released by overflow from the divider 1. hcf.5 = 1 hold mode was released by underflow from the timer 1. hcf.6 and hcf.7 are reserved. 6.15.5 event flag (evf) the event flag is organized as a 8 - bit binary register (evf.0 to evf.7). it is set by hardware and reset by clr evf,#i ins truction or the occurrence of an interrupt. the bit descriptions are as follows: r r r evf 0 1 2 3 4 5 r r 6 7 note: r means read only.
preliminary w742e81a/W742C81A - 24 - evf.0 = 1 overflow from divider 0 occurred. evf.1 = 1 underflow from ti mer 0 occurred. evf.2 = 1 signal change at port rc occurred. evf.3 is reserved. evf.4 = 1 overflow from divider 1 occurred. evf.5 & evf.6 are reserved. evf.7 = 1 underflow from timer 1 occurred. 6.16 reset function the w742e81a/W742C81A is reset either by a power - on reset or by using the external res pin. the initial state of the w742e81a/W742C81A after the reset function is executed is described below. table 4 the initial state after the reset function is executed p rogram counter (pc) 000h wdtr registers reset buzcr registers reset acc, cf, zf registers reset mr0, mr1, page registers reset psr0, scr, tm0, tm1 registers reset ief, hef, hcf, pef, evf, sef flags reset wrp, dbkr, page registers reset timer 0 inpu t clock f osc /4 timer 1 input clock f osc mfp output low dtmf output hi - z input/output ports ra, rb, rd input mode output port re & rf high ra, rb ports output type cmos type rc ports pull - high resistors disable input clock of the watchdog timer f os c /2048 lcd display off
preliminary w742e81a/W742C81A publication release date : april 2000 - 25 - revision a1 6.17 input/output ports ra, rb & rd port ra consists of pins ra.0 to ra.3. port rb consists of pins rb.0 to rb.3. port rd consists of pins rd.0 to rd.3. at initial reset, input/output ports ra, rb and rd are all in input mode. when ra, rb are used as output ports, cmos or nmos open drain output type can be selected by the pm0 register. but when rd is used as output port, the output type is just fixed to be cmos output type. each pin of port ra, rb and rd can be specified as input or out put mode independently by the pm1, pm2 and pm5 registers. the mova r, ra or mova r, rb or mova r, rd instructions operate the input functions and the mov ra, r or mov rb, r or mov rd, r operate the output functions. for more details, refer to the instructi on table and figure 6 - 10 and figure 6 - 11 . input/output pin of the ra(rb) i/o pin ra.n(rb.n) data bus buffer output pm0.0(pm0.1) pm1.n (pm2.n) mova r,ra(mova r,rb) instruction mov ra,r(mov rb,r) instruction enable enable figure 6 - 10 architecture of ra (rb) input/output pins input/output pin of the rd i/o pin rd.n data bus buffer output pm5.n mova r,rd instruction mov rd,r instruction enable enable figure 6 - 11 architecture of rd input/output pins 6.17.1 port mode 0 register (pm0) the port mode 0 register is organized as 4 - bit binary register (pm0.0 to pm0.3). pm0 can be used to
preliminary w742e81a/W742C81A - 26 - determin e the structure of the input/output ports; it is controlled by the mov pm0, #i instruction. the bit descriptions are as follows: pm0 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 ra port is cmos output type. bit 0 = 1 ra port is nmos open drain output type. bit 1 = 0 rb port is cmos output type. bit 1 = 1 rb port is nmos open drain output type. bit 2 = 0 rc port pull - high resistor is disabled. bit 2 = 1 rc port pull - high resistor is enabled. bit 3 is r eserved. 6.17.2 port mode 1 register (pm1) the port mode 1 register is organized as 4 - bit binary register (pm1.0 to pm1.3). pm1 can be used to control the input/output mode of port ra. pm1 is controlled by the mov pm1, #i instruction. the bit descriptions are as follows: pm1 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 ra.0 works as output pin; bit 0 = 1 ra.0 works as input pin bit 1 = 0 ra.1 works as output pin; bit 1 = 1 ra.1 works as input pin bit 2 = 0 ra.2 works as output pin; bit 2 = 1 ra.2 works as input pin bit 3 = 0 ra.3 works as output pin; bit 3 = 1 ra.3 works as input pin at initial reset, port ra is input mode (pm1 = 1111b). 6.17.3 port mode 2 register (pm2) the port mode 2 register is organize d as 4 - bit binary register (pm2.0 to pm2.3). pm2 can be used to control the input/output mode of port rb. pm2 is controlled by the mov pm2, #i instruction. the bit descriptions are as follows: pm2 w w w 0 1 2 w 3 note: w me ans write only. bit 0 = 0 rb.0 works as output pin; bit 0 = 1 rb.0 works as input pin bit 1 = 0 rb.1 works as output pin; bit 1 = 1 rb.1 works as input pin bit 2 = 0 rb.2 works as output pin; bit 2 = 1 rb.2 works as input pin bit 3 = 0 rb.3 w orks as output pin; bit 3 = 1 rb.3 works as input pin at initial reset, the port rb is input mode (pm2 = 1111b).
preliminary w742e81a/W742C81A publication release date : april 2000 - 27 - revision a1 6.17.4 port mode 5 register (pm5) the port mode 5 register is organized as 4 - bit binary register (pm5.0 to pm5.3). pm5 can be used to control the input/output mode of port rd. pm5 is controlled by the mov pm5, #i instruction. the bit descriptions are as follows: pm5 w w w 0 1 2 w 3 note: w means write only. bit 0 = 0 rd.0 works as output pin; bit 0 = 1 rd.0 works as input pin bit 1 = 0 rd.1 works as output pin; bit 1 = 1 rd.1 works as input pin bit 2 = 0 rd.2 works as output pin; bit 2 = 1 rd.2 works as input pin bit 3 = 0 rd.3 works as output pin; bit 3 = 1 rd.3 works as input pin at initial reset, t he port rd is input mode (pm5 = 1111b). 6.18 input ports rc port rc consists of pins rc.0 to rc.3. each pin of port rc can be connected to a pull - up resistor, which is controlled by the port mode 0 register (pm0). when the pef, hef, and ief corresponding to th e rc port are set, a signal change at the specified pins of port rc will execute the hold mode release or interrupt subroutine. port status register 0 (psr0) records the status of ports rc, i.e., any signal changes on the pins that make up the ports. psr0 can be read out and cleared by the mov r, psr0, and clr psr0 instructions. in addition, the falling edge signal on the pin of port rc specified by the instruction mov sef, #i will cause the device to exit the stop mode . refer to figure 6 - 12 and the instruction table for more details.
preliminary w742e81a/W742C81A - 28 - signal change detector pef.0 d ck q r psr0.0 psr0.2 d ck q r data bus rc.0 psr0.3 d ck q r pef.3 reset clr psr0 hcf.2 int 2 reset clr evf, #i evf.2 hef.2 ief.2 falling edge detector falling edge detector falling edge detector falling edge detector sef.0 sef.1 sef.2 sef.3 to wake up stop mode signal change detector d ck q r psr0.1 rc.1 pef.1 signal change detector d ck q r pef.2 rc.2 signal change detector rc.3 pm0.2 pm0.2 pm0.2 pm0.2 mov pef, #i figure 6 - 12 architecture of input ports rc 6.18.1 port status register 0 (psr0) port status register 0 is organize d as 4 - bit binary register (psr0.0 to psr0.3). psr0 can be read or cleared by the mova r, psr0, and clr psr0 instructions. the bit descriptions are as follows: r r r r 0 1 2 3 psr0 note: r means read only.
preliminary w742e81a/W742C81A publication release date : april 2000 - 29 - revision a1 bit 0 = 1 s ignal change at rc.0 bit 1 = 1 signal change at rc.1 bit 2 = 1 signal change at rc.2 bit 3 = 1 signal change at rc.3 6.19 output port re & rf output port re is used as an output of the internal rt port. when the mov re, r instruction is executed, the d ata in the ram will be output to port rt through port re. it provides a high sink current to drive an led. rf port is just used as a output port. when the mov rf, r instruction is executed, the data in the ram will be output to rf. 6.20 dtmf output pin (dtmf) t his pin should output the dual tone multi - frequency signal from the dtmf generator. there is the dtmf register that can specify the wanted low/high frequency. and control whether the dual tone will be output or not. the tones are divided into two groups (r ow group and col group) and one tone from each group is selected to represent a digit. the relation between the dtmf signal and the corresponding touch tone keypad is shown in figure 6 - 13 . row/col frequency r1 697 hz r2 770 hz r3 852 hz r4 941 hz c1 1209 hz c2 1336 hz c3 1477 hz c4 1633 hz figure 6 - 13 the relation between the touch tone keypad and the frequency 6.20.1 dtmf register dtmf register is organized as 4 - bit bin ary register. by controlling the dtmf register, one tone of the low/high group can be selected. the mov dtmf,r instruction can specify the wanted tones. the bit descriptions are as follows: w w w w 0 1 2 3 dtmf note: w m eans write only. 1 2 3 a 4 5 6 b 7 8 9 c * 0 # d r1 r2 r3 r4 c1 c2 c3 c4
preliminary w742e81a/W742C81A - 30 - b3 b2 b1 b0 selected tone x x 0 0 1209 hz high x x 0 1 1336 hz group x x 1 0 1477 hz x x 1 1 1633 hz 0 0 x x 697 hz low 0 1 x x 770 hz group 1 0 x x 852 hz 1 1 x x 941 hz note: x means this bit do not care. 6.20.2 dual tone contro l register (dtcr) dual tone control register is organized as 4 - bit binary register. the output of the dual or single tone will be controlled by this register. the mov dtcr,#i instruction can specify the wanted status. the bit descriptions are as follows: w w w 0 1 2 3 dtcr note: w means write only. bit 0 = 1 low group tone output is enabled. bit 1 = 1 high group tone output is enabled. bit 2 = 1 dtmf output is enabled. when bit 2 is reset to 0, the dtmf output pin will be hi - z state. bit 3 is reserved. 6.21 mfp output pin (mfp) the mfp output pin can output the timer 1 clock or the modulation frequency; the output of the pin is determined by bit 0 of buzcr (buzcr.0). the organization of mr1 is shown in figure 6 - 7 . when bit 0 of buzcr is reset to "0," the mfp output can deliver a modulation output in any combination of one signal from among dc, 4096 hz, 2048 hz, and one or more signals from among 128 hz, 64 hz, 8 hz, 4 hz, 2 hz, or 1 hz (when using a 32.768 khz crystal). the mov mfp, #i instruction is used to specify the modulation output combination. the data specified by the 8 - bit operand and the mfp output pin are shown in next page.
preliminary w742e81a/W742C81A publication release date : april 2000 - 31 - revision a1 table 5 the relation between the mfp output frequncy and the data specified by 8 - bit operand (fosc = 32.768 khz) r7 r6 r5 r4 r3 r2 r1 r0 function 0 0 0 0 0 0 low level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 0 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 high level 0 0 0 0 0 1 128 hz 0 0 0 0 1 0 64 hz 0 1 0 0 0 1 0 0 8 hz 0 0 1 0 0 0 4 hz 0 1 0 0 0 0 2 hz 1 0 0 0 0 0 1 hz 0 0 0 0 0 0 2048 hz 0 0 0 0 0 1 2048 hz * 128 hz 0 0 0 0 1 0 2048 hz * 64 hz 1 0 0 0 0 1 0 0 2048 hz * 8 hz 0 0 1 0 0 0 2048 hz * 4 hz 0 1 0 0 0 0 2048 hz * 2 hz 1 0 0 0 0 0 2048 hz * 1 hz 0 0 0 0 0 0 4096 hz 0 0 0 0 0 1 4096 hz * 128 hz 0 0 0 0 1 0 4096 hz * 64 hz 1 1 0 0 0 1 0 0 4096 hz * 8 hz 0 0 1 0 0 0 4096 hz * 4 hz 0 1 0 0 0 0 4096 hz * 2 hz 1 0 0 0 0 0 4096 hz * 1 hz
preliminary w742e81a/W742C81A - 32 - 6.22 lcd controller/driver the w742e81a/W742C81A can directly drive an lcd with 40 segment output pins and 4 common output pins for a total of 40 4 dots. the lcd driving mode is 1/3 bias 1/4 duty. the alternating frequency of the lcd can be set as fw/64, fw/128, fw/256, or fw/512. the structure of the lcd alternating frequency (f lcd ) is shown in the figure 6 - 14 . q1 q2 q3 q4 q5 q6 q7 q8 q9 fw selector fw/512 fw/256 fw/128 fw/64 fs or fosc/128 (by dual or single clock option) f lcd figure 6 - 14 lcd alternating frequency (flcd) circuit diagram fw = 32.768 khz, the lcd frequency is as shown in the table below. table 6 the relat ionship between the flcd and the duty cycle lcd frequency fw/64 (512hz) fw/128 (256hz) fw/256 (128hz) fw/512 (64hz) 1/4 duty 128 hz 64 hz 32 hz 16 hz corresponding to the 40 lcd drive output pins, there are 40 lcd data ram segments. instructions such as mov lpl,r, mov lph,r, mov @lp,r, and mov r,@lp are used to control the lcd data ram. the data in the lcd data ram are transferred to the segment output pins automatically without program control. when the bit value of the lcd data ram is "1," the lcd is tu rned on. when the bit value of the lcd data ram is "0," lcd is turned off. the contents of the lcd data ram (lcdr) are sent out through the segment0 to segment39 pins by a direct memory access. the relation between the lcd data ram and segment/common pins is shown below. table 7 the reation between the lcdr and segment/common pins used as lcd drive output pins com3 com2 com1 com0 lcd data ram output pin bit 3 bit 2 bit 1 bit 0 lcdr00 seg0 0/1 0/1 0/1 0/1 lcdr01 seg1 0/1 0/1 0/1 0/1 : : : : : : : : : : : : lcdr26 seg38 0/1 0/1 0/1 0/1 lcdr27 seg39 0/1 0/1 0/1 0/1
preliminary w742e81a/W742C81A publication release date : april 2000 - 33 - revision a1 the lcdon instruction turns the lcd display on (even in hold mode), and the lcdoff instruction turns the lcd display off. at initial reset, all the lcd segments ar e unlit. when the initial reset state ends, the lcd display is turned off automatically. to turn on the lcd display, the instruction lcdon must be executed. 6.22.1 lcd ram addressing method there are 40 lcd rams (lcdr00 - lcdr27) that should be indirectly address ed. the lcd ram pointer (lp) is used to point to the address of the wanted lcd ram. the lp is organized as 6 - bit binary register. the mov lpl,r and mov lph,r instructions can load the lcd ram address to the lp from r. the mov @lp,r and mov r,@lp instructio ns can access the pointed lcd ram content. 6.22.2 the output waveforms for the lcd driving mode 1/3 bias 1/4 duty lighting system (example) normal operating mode com0 vdd2 vdd1 vss vdd3 vdd2 vdd1 vss vdd3 com1 com2 vdd2 vdd1 vss vdd3 vdd2 vdd1 vss vdd3 com3 vdd2 vdd1 vss vdd3 vdd2 vdd1 vss vdd3 lcd driver outputs for only seg. on com0 side being lit lcd driver outputs for only seg. on com1 side being lit
preliminary w742e81a/W742C81A - 34 - continued vdd2 vdd1 vss vdd3 vdd2 vdd1 vss vdd3 lcd driver outputs for seg. on com0, com1 sides being lit lcd driver outputs for seg. on com1, com2,3 sides being lit vdd2 vdd1 vss vdd3 vdd2 vdd1 vss vdd3 lcd driver outputs for seg. on com1 com2 sides being lit lcd driver outputs for seg. on com0 com2,3 sides being lit vdd2 vdd1 vss vdd3 lcd driver outputs for seg. on com0 com1,2,3 sides being lit the power connections for the 1/3 bias 1/4 duty lcd driving mode are shown below. dh1 dh2 vss vdd1 vdd vdd2 0.1uf 0.1uf vdd = 3.0 v c h i p 1/3 bias at vdd = 3.0 v
preliminary w742e81a/W742C81A publication release date : april 2000 - 35 - revision a1 6.23 mode description the built - i n program code memory of the w742e81a/W742C81A is the eeprom structure. this memory can be programmed, erased and verified through the vpp, mode and data pins. 7. absolute maximum rat ings parameter rating unit supply voltage to ground potential - 0.3 to +7.0 v applied input/output voltage - 0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature - 55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect t he life and reliability of the device. 8. dc characteristics (v dd - v ss = 3.0 v, fm = 3.58 mhz, fs = 32.768 khz, t a = 25 c, lcd on; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v dd - 2.4 - 3.8 v op. current (crystal type) i op1 no load (ext - v) in dual - clock normal operation - 0.9 2.5 ma op. current (crystal type) i op3 no load (ext - v) in dual - clock slow operation and fm is stopped - 20 30 m a hold current (crystal type) i hm1 hold mode no load (ext - v) in dual - clock normal operation - - 450 m a hold current (crystal type) i hm3 hold mode no load (ext - v) in dual - clock slow operation and fm is stopped - 15 30 m a stop current (crystal type) i sm1 stop mode no load (ext - v) in dual - clock normal operation - 1 2 m a
preliminary w742e81a/W742C81A - 36 - dc characteristics, continued parameter sym. conditions min. typ. max. unit input low voltage v il - v ss - 0.3 v dd v input high voltage v ih - 0.7 v dd - v dd v mfp output low voltage v ml i ol = 3.5 ma - - 0.4 v mfp ou tput high voltage v mh i oh = 3.5 ma 2.4 - - v port ra, rb, rd and rf output low voltage v abl i ol = 2.0 ma - - 0.4 v port ra, rb, rd and rf output high voltage v abh i oh = 2.0 ma 2.4 - - v lcd supply current i lcd all seg. on - - 6 m a seg0 - seg39 sink c urrent (used as lcd output) i ol1 v ol = 0.4v v lcd = 0.0v 90 - - m a seg0 - seg39 drive current (used as lcd output) i oh1 v oh = 2.4v v lcd = 3.0v 90 - - m a port re sink current i el v ol = 0.9v 9 - - ma port re source current i eh v oh = 2.4v 0.4 1.2 - ma dtmf output dc level v tdc r l = 5 k w , v dd = 2.5 to 3.8v 1.1 - 2.8 v dtmf distortion t hd r l = 5 k w , v dd = 2.5 to 3.8v - - 30 - 23 db dtmf output voltage v to low group, r l = 5 k w 130 150 170 mvrms pre - emphasis col/row 1 2 3 db dtmf output sink current i tl v to = 0.5v 0.2 - - ma pull - up resistor r c port rc 100 350 1000 k w res pull - up resistor r res - 20 100 500 k w 9. ac characteristics parameter sym. conditions min. typ. max. unit op. frequency f osc crystal type - 3.58 - mhz instruction cycle time t i one ma chine cycle - 4/f osc - s reset active width t raw f osc = 32.768 khz 1 - - m s interrupt active width t iaw f osc = 32.768 khz 1 - - m s
preliminary w742e81a/W742C81A publication release date : april 2000 - 37 - revision a1 10. instruction set tabl e symbol description acc: accumulator acc.n: accumulator bit n wr: working register wrp: wr pag e register page: page register dbkr: data bank register rompr: rom page register mr0: mode register 0 mr1: mode register 1 pm0: port mode 0 pm1: port mode 1 pm2: port mode 2 pm5: port mode 5 psr0: port status register 0 r: memory (ram) of addres s r wdtr: watchdog timer register lpl: lcd data ram pointer lph: lcd data ram pointer r.n: memory bit n of address r scr: system control register buzcr: buzzer control register ra: i/o port ra rc: i/o port rc dtmf: dtmf register d tcr: mtmf control pin mfp: mfp output pin
preliminary w742e81a/W742C81A - 38 - symbol description, continued i: constant parameter l: branch or jump address cf: carry flag zf: zero flag pc: program counter tm0l: low nibble of the timer 0 counter tm0h: high nibble of the timer 0 cou nter tm1l: low nibble of the timer 1 counter tm1h: high nibble of the timer 1 counter tab0: look - up table address buffer 0 tab1: look - up table address buffer 1 tab2: look - up table address buffer 2 tab3: look - up table address buffer 3 ief.n: interrup t enable flag n hcf.n: hold mode release condition flag n hef.n: hold mode release enable flag n sef.n: stop mode wake - up enable flag n pef.n: port enable flag n evf.n: event flag n ! =: not equal &: and ^: or ex: exclusive or ? : transfer directi on, result [page*10h+()]: contents of address page (bit2, bit1, bit0)*10h+() [p()]: contents of port p
preliminary w742e81a/W742C81A publication release date : april 2000 - 39 - revision a1 machine code mnemonic function flag affected w/c arithmetic 0001 1000 0xxx xxxx add r, acc acc ? (r) + (acc) zf, cf 1/1 0001 1100 iiii nnnn add wrn, #i acc ? (wrn) + i zf, cf 1/1 0001 1001 0xxx xxxx addr r, acc acc, r ? (r) + (acc) zf, cf 1/1 0001 1101 iiii nnnn addr wrn, #i acc, wrn ? (wrn) + i zf, cf 1/1 0000 1000 0xxx xxxx adc r, acc acc ? (r) + (acc) + (cf) zf, cf 1/1 0000 1100 iiii nn nn adc wrn, #i acc ? (wrn) + i + (cf) zf, cf 1/1 0000 1001 0xxx xxxx adcr r, acc acc, r ? (r) + (acc) + (cf) zf, cf 1/1 0000 1101 iiii nnnn adcr wrn, #i acc, wrn ? (wrn) + i + (cf) zf, cf 1/1 0010 1000 0xxx xxxx adu r, acc acc ? (r) + (acc) zf 1/1 0010 110 0 iiii nnnn adu wrn, #i acc ? (wrn) + i zf 1/1 0010 1001 0xxx xxxx adur r, acc acc, r ? (r) + (acc) zf 1/1 0010 1101 iiii nnnn adur wrn, #i acc, wrn ? (wrn) + i zf 1/1 0001 1010 0xxx xxxx sub r, acc acc ? (r) - (acc) zf, cf 1/1 0001 1110 iiii nnnn sub wrn, #i acc ? (wrn) - i zf, cf 1/1 0001 1011 0xxx xxxx subr r, acc acc, r ? (r) - (acc) zf, cf 1/1 0001 1111 iiii nnnn subr wrn, #i acc, wr ? (wr) - i zf, cf 1/1 0000 1010 0xxx xxxx sbc r, acc acc ? (r) - (acc) - (cf) zf, cf 1/1 0000 1110 iiii nnnn sbc wrn, #i acc ? (wrn) - i - (cf) zf, cf 1/1 0000 1011 0xxxxxxx sbcr r, acc acc, r ? (r) - (acc) - (cf) zf, cf 1/1 0000 1111 iiii nnnn sbcr wrn, #i acc, wrn ? (wrn) - i - (cf) zf, cf 1/1 0100 1010 0xxx xxxx inc r acc, r ? (r) + 1 zf, cf 1/1 0100 1010 1xxx x xxx dec r acc, r ? (r) - 1 zf, cf 1/1
preliminary w742e81a/W742C81A - 40 - instruction set, continued machine code mnemonic function flag affected w/c logic 0010 1010 0xxx xxxx anl r, acc acc ? (r) & (acc) zf 1/1 0010 1110 iiii nnnn anl wrn, #i acc ? (wrn) & i zf 1/1 0010 10 11 0xxx xxxx anlr r, acc acc, r ? (r) & (acc) zf 1/1 0010 1111 iiii nnnn anlr wrn, #i acc, wrn ? (wrn) & i zf 1/1 0011 1010 0xxx xxxx orl r, acc acc ? (r) (acc) zf 1/1 0011 1110 iiii nnnn orl wrn, #i acc ? (wrn) i zf 1/1 0011 1011 0xxx xxxx orlr r , acc acc, r ? (r) (acc) zf 1/1 0011 1111 iiii nnnn orlr wrn, #i acc, wrn ? (wrn) i zf 1/1 0011 1000 0xxx xxxx xrl r, acc acc ? (r) ex (acc) zf 1/1 0011 1100 iiii nnnn xrl wrn, #i acc ? (wrn) ex i zf 1/1 0011 1001 0xxx xxxx xrlr r, acc acc, r ? (r) e x (acc) zf 1/1 0011 1101 iiii nnnn xrlr wrn, #i acc, wrn ? (wrn) ex i zf 1/1 branch 0111 0 aaa aaaa aaaa jmp l pc12~pc0 ? (rompr) 800h+l10~l0 1/1 1000 0 aaa aaaa aaaa jb0 l pc10~pc0 ? l10~l0; if acc.0 = "1" 1/1 1001 0 aaa aaaa aaaa jb1 l pc 10~pc0 ? l10~l0; if acc.1 = "1" 1/1 1010 0 aaa aaaa aaaa jb2 l pc10~pc0 ? l10~l0; if acc.2 = "1" 1/1 1011 0 aaa aaaa aaaa jb3 l pc10~pc0 ? l10~l0; if acc.3 = "1" 1/1 1110 0 aaa aaaa aaaa jz l pc10~pc0 ? l10~l0; if acc = 0 1/1 1100 0 aaa aaaa aaaa j nz l pc10~pc0 ? l10~l0; if acc ! = 0 1/1 1111 0 aaa aaaa aaaa jc l pc10~pc0 ? l10~l0; if cf = "1" 1/1 1101 0 aaa aaaa aaaa jnc l pc10~pc0 ? l10~l0; if cf != "1" 1/1 0100 1000 0xxx xxxx dskz r acc, r ? (r) - 1; pc ? (pc) + 2 if acc = 0 zf, cf 1/1 0100 1000 1xxx xxxx dsknz r acc, r ? (r) - 1; pc ? (pc) + 2 if acc != 0 zf, cf 1/1 1010 1000 0xxx xxxx skb0 r pc ? (pc) + 2 if r.0 = "1" 1/1 1010 1000 1xxx xxxx skb1 r pc ? (pc) + 2 if r.1 = "1" 1/1 1010 1001 0xxx xxxx skb2 r pc ? (pc) + 2 if r.2 = "1" 1/1 1010 1001 1xxx xxxx skb3 r pc ? (pc) + 2 if r.3 = "1" 1/1
preliminary w742e81a/W742C81A publication release date : april 2000 - 41 - revision a1 instruction set, continued machine code mnemonic function flag affected w/c data move 0001 0000 0000 iiii mov acc, #i acc ? i zf 1/1 1110 1nnn nxxx xxxx mov wrn, r wrn ? (r) 1/1 1001 1001 iiii nnnn mov wrn, #i wrn ? i 1/1 1111 1nnn nxxx xxxx mov r, wrn r ? (wrn) 1/1 0110 1nnn nxxx xxxx mova wrn, r acc, wrn ? (r) zf 1/1 0111 1nnn nxxx xxxx mova r, wrn acc, r ? (wrn) zf 1/1 0101 1001 1xxx xxxx mov r, acc r ? (acc) 1/1 0100 11 10 1xxx xxxx mov acc, r acc ? (r) zf 1/1 1011 1 iii i xxx xxxx mov r, #i r ? i 1/1 1100 1nnn n000 qqqq mov wrn, @wrq wrn ? [(dbkr) 80h+(page)x10h +(wrq)] 1/2 1101 1nnn n000 qqqq mov @wrq, wrn [(dbkr) 80h+(page)x10h +(wrq)] ? wrn 1/2 1000 1100 0xxx xxxx mov tab0, r tab0 ? (r) 1/1 1000 1100 1xxx xxxx mov tab1, r tab1 ? (r) 1/1 1000 1110 0xxx xxxx mov tab2, r tab2 ? (r) 1/1 1000 1110 1xxx xxxx mov tab3, r tab3 ? (r) 1/1 1000 1101 0xxx xxxx movc r r ? [(tab3) 1000h+(tab2)x100h+(tab1) x10h + (tab0)] 1/2 input & output 0101 1011 0xxx xxxx mova r, ra acc, r ? [ra] zf 1/1 0101 1011 1xxx xxxx mova r, rb acc, r ? [rb] zf 1/1 0100 1011 0xxx xxxx mova r, rc acc, r ? [rc] zf 1/1 0100 1011 1xxx xxxx mova r, rd acc, r ? [rd] zf 1/1 0101 1010 0xxx xxxx mov ra, r [ra] ? (r) 1/1 0101 1010 1xxx xxxx mov rb, r [rb] ? (r) 1/1 0100 1010 0xxx xxxx mov rc, r [rc] ? (r) 1/1 1010 1100 1xxx xxxx mov rd, r [rd] ? (r) 1/1 0101 1110 0xxx xxxx mov re, r [re] ? (r) 1/1 1010 1110 0xxx xxxx mov rf, r [rf] ? (r) 1/1
preliminary w742e81a/W742C81A - 42 - instruction set, continued machine code mnemonic function flag affected w/c flag & register 0101 1111 1xxx xxxx mova r, page acc, r ? page (page register) zf 1/1 0101 1110 1xxx xxxx mov page, r page ? (r) 1/1 0101 0110 1000 0 iii mov page, #i pa ge ? i 1/1 1001 1101 1xxx xxxx mov r, wrp r ? wrp 1/1 1001 1100 1xxx xxxx mov wrp, r wrp ? (r) 1/1 0011 0101 1000 iiii mov wrp, #i wrp ? i 1/1 1001 1101 0000 nnnn mov wrn,dbkr wrn ? dbkr 1/1 1001 1111 0000 nnnn mov wrn,tm1 wrn ? tm1.4 - tm1.7, acc ? tm1.0 - tm1.3 1/1 1001 1100 0000 nnnn mov dbkr, wrn dbkr ? wrn 1/1 0011 0101 0000 i iii mov dbkr, #i dbkr ? i 1/1 0011 0100 0000 0i ii mov rompr, #i rompr ? i 1/1 1000 1000 0xxx xxxx mov rompr, r rompr ? (r) 1/1 1000 1001 0xxx xxxx mov r, rompr r ? (ro mpr) 1/1 0101 1001 0xxx xxxx mova r, cf acc.0, r.0 ? cf zf 1/1 0101 1000 0xxx xxxx mov cf, r cf ? (r.0) cf 1/1 0100 1001 0xxx xxxx mova r, hcfl acc, r ? hcf.0~hcf.3 zf 1/1 0100 1001 1xxx xxxx mova r, hcfh acc, r ? hcf.4~hcf.7 zf 1/1 0101 0011 0000 iiii mov pm0, #i port mode 0 ? i 1/1 0101 0111 0000 iiii mov pm1, #i port mode 1 ? i 1/1 0101 0111 1000 iiii mov pm2, #i port mode 2 ? i 1/1 0011 0111 1000 iiii mov pm5, #i port mode 5 ? i 1/1 0100 0000 i00i 0 iii clr evf, #i clear event flag if in = 1 1/1 0101 1101 0xxx xxxx mova r, evfl r ? evf.0 - evf.3 1/1 0101 1101 1xxx xxxx mova r, evfh r ? evf.4 - evf.7 1/1 0100 0001 i00i 0 iii mov hef, #i set/reset hold mode release enable flag 1/1 0101 0001 i00i 0 iii mov ief, #i set/reset interrupt ena ble flag 1/1 0100 0011 0000 iiii mov pef, #i set/reset port enable flag 1/1 0101 0010 0000 iiii mov sef, #i set/reset stop mode wake - up enable flag for rc port 1/1
preliminary w742e81a/W742C81A publication release date : april 2000 - 43 - revision a1 instruction set, continued machine code mnemonic function flag affected w/c flag & register 0101 0100 0000 i0ii mov scr, #i scr ? i 1/1 0100 1111 0xxx xxxx mova r, psr0 acc, r ? port status register 0 zf 1/1 0100 0010 0000 0000 clr psr0 clear port status register 0 1/1 0101 0000 0100 0000 set cf set carry flag cf 1/1 0101 00 00 0000 0000 clr cf clear carry flag cf 1/1 0001 0111 0000 0000 clr divr0 clear the last 4 - bit of the divider 0 1/1 0101 0101 1000 0000 clr divr1 clear the last 4 - bit of the divider 1 1/1 0101 0110 0000 iiii mov wdtr, #i wdtr ? i 1/1 0101 1111 0 xxx xxxx mova r,wdtr acc, r ? watchdog timer register 1/1 0001 0111 1000 0000 clr wdt clear watchdog timer 1/1 dtmf 1001 1110 1xxx xxxx mov dtmf,r dtmf ? (r) 1/1 0011 0100 1000 0iii mov dtcr,i dtcr ? i 1/1 shift & rotate 0100 1101 0xxx xxxx shrc r acc.n, r.n ? (r.n+1); acc.3, r.3 ? 0; cf ? r.0 zf, cf 1/1 0100 1101 1xxx xxxx rrc r acc.n, r.n ? (r.n+1); acc.3, r.3 ? cf; cf ? r.0 zf, cf 1/1 0100 1100 0xxx xxxx shlc r acc.n, r.n ? (r.n - 1); acc.0, r.0 ? 0; cf ? r.3 zf, cf 1/1 0100 1100 1xxx xxxx rlc r acc.n, r.n ? (r.n - 1); acc.0, r.0 ? cf; cf ? r.3 zf, cf 1/1
preliminary w742e81a/W742C81A - 44 - instruction set, continued machine code mnemonic function flag affected w/c lcd 1001 1000 0xxx xxxx mov lpl, r lpl ? (r) 1/1 1001 1000 1xxx xxxx mov lph, r lph ? (r) 1/1 1001 1010 0xxx xxxx mov @lp, r [(lph) 10h+(lpl)] ? (r) 1/1 1001 1011 0xxx xxxx mov r, @lp r ? [ (lph) 10h+(lpl)] 1/1 0000 0010 0000 0000 lcdon lcd on 1/1 0000 0010 1000 0000 lcdoff lcd off 1/1 mfp 0011 0110 0000 000 i mov buzcr, #i buzcr ? i 1/1 1000 1010 0xxx xxxx mov buzcr, r buzcr ? (r) 1/1 1000 1011 0xxx xxxx mov r,buzcr r ? (buzcr) 1/1 0001 0010 iiii iiii mov mfp, #i [mfp] ? i 1/1 timer 1010 1010 0xxx xxxx mov tm0l, r tm0l ? (r) 1/1 1010 1010 1xxx xxxx mov tm0h, r tm0h ? (r) 1/1 1010 1011 0xxx xxxx mov tm1l, r tm1l ? (r) 1/1 1010 1011 1xxx xxxx mov tm1h, r tm1h ? (r) 1/1 0001 0011 1000 i00i mov mr0,#i mr0 ? (r) 1/1 0001 0011 0000 iiii mov mr1,#i mr1 ? (r) 1/1 other 0000 0000 1000 0000 hold enter hold mode 1/1 0000 0000 1100 0000 stop enter stop mode 1/1 0000 0000 0000 0000 nop no operation 1/1 0101 0000 1100 0000 en int enable interrupt function 1/1 0101 0000 1000 0000 dis int disable interrupt function 1/1 subroutine 0110 0aaa aaaa aaaa call l push stack: s tack < - pc+1, tab0, tab1, tab2, tab3, dbkr, wrp, rompr, page, acc, cf; pc12~pc0< - (rompr)x800h+l10~l0 1/1 0000 0001 iiii iiii rtn #i ( pc) < - stack; pop other register by i table setting (refer to table 8) 1/1
preliminary w742e81a/W742C81A publication release date : april 2000 - 45 - revision a1 tabl e 8 the bit definition of rtn bit definition of i i = 0000 0000 pop pc from stack only bit0 = 1 pop pc and tab0, tab1, tab2, tab3 from stack bit1 = 1 pop pc and dbkr from stack bit2 = 1 pop pc and wrp from stack bit3 = 1 pop pc and rompr from stack bit4 = 1 pop pc and page from stack bit5 = 1 pop pc and acc from stack bit6 = 1 pop pc and cf from stack headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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